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Lines 18-39
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#ifdef USE_ATOMICS_IA32 |
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#ifdef USE_ATOMICS_IA32 |
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#ifdef __INTEL_COMPILER |
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# define barrier() __memory_barrier() |
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#else |
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# define barrier() asm volatile ("": : :"memory") |
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#endif |
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APR_DECLARE(apr_status_t) apr_atomic_init(apr_pool_t *p) |
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APR_DECLARE(apr_status_t) apr_atomic_init(apr_pool_t *p) |
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{ |
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{ |
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return APR_SUCCESS; |
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return APR_SUCCESS; |
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} |
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} |
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APR_DECLARE(apr_uint32_t) apr_atomic_read32(volatile apr_uint32_t *mem) |
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APR_DECLARE(apr_uint32_t) apr_atomic_read32(apr_uint32_t *mem) |
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{ |
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{ |
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barrier(); |
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return *mem; |
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return *mem; |
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} |
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} |
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APR_DECLARE(void) apr_atomic_set32(volatile apr_uint32_t *mem, apr_uint32_t val) |
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APR_DECLARE(void) apr_atomic_set32(apr_uint32_t *mem, apr_uint32_t val) |
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{ |
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{ |
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*mem = val; |
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*mem = val; |
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barrier(); |
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} |
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} |
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APR_DECLARE(apr_uint32_t) apr_atomic_add32(volatile apr_uint32_t *mem, apr_uint32_t val) |
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APR_DECLARE(apr_uint32_t) apr_atomic_add32(apr_uint32_t *mem, apr_uint32_t val) |
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{ |
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{ |
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asm volatile ("lock; xaddl %0,%1" |
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asm volatile ("lock; xaddl %0,%1" |
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: "=r" (val), "=m" (*mem) |
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: "=r" (val), "=m" (*mem) |
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APR_DECLARE(apr_uint32_t) apr_atomic_add
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return val; |
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return val; |
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} |
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} |
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APR_DECLARE(void) apr_atomic_sub32(volatile apr_uint32_t *mem, apr_uint32_t val) |
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APR_DECLARE(void) apr_atomic_sub32(apr_uint32_t *mem, apr_uint32_t val) |
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{ |
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{ |
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asm volatile ("lock; subl %1, %0" |
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asm volatile ("lock; subl %1, %0" |
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: /* no output */ |
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: /* no output */ |
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Lines 50-61
APR_DECLARE(void) apr_atomic_sub32(volat
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: "memory", "cc"); |
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: "memory", "cc"); |
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} |
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} |
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APR_DECLARE(apr_uint32_t) apr_atomic_inc32(volatile apr_uint32_t *mem) |
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APR_DECLARE(apr_uint32_t) apr_atomic_inc32(apr_uint32_t *mem) |
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{ |
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{ |
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return apr_atomic_add32(mem, 1); |
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return apr_atomic_add32(mem, 1); |
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} |
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} |
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APR_DECLARE(int) apr_atomic_dec32(volatile apr_uint32_t *mem) |
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APR_DECLARE(int) apr_atomic_dec32(apr_uint32_t *mem) |
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{ |
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{ |
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unsigned char prev; |
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unsigned char prev; |
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APR_DECLARE(int) apr_atomic_dec32(volati
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return prev; |
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return prev; |
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} |
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} |
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APR_DECLARE(apr_uint32_t) apr_atomic_cas32(volatile apr_uint32_t *mem, apr_uint32_t with, |
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APR_DECLARE(apr_uint32_t) apr_atomic_cas32(apr_uint32_t *mem, apr_uint32_t with, |
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apr_uint32_t cmp) |
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apr_uint32_t cmp) |
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{ |
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{ |
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apr_uint32_t prev; |
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apr_uint32_t prev; |
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APR_DECLARE(apr_uint32_t) apr_atomic_cas
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return prev; |
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return prev; |
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} |
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} |
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APR_DECLARE(apr_uint32_t) apr_atomic_xchg32(volatile apr_uint32_t *mem, apr_uint32_t val) |
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APR_DECLARE(apr_uint32_t) apr_atomic_xchg32(apr_uint32_t *mem, apr_uint32_t val) |
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{ |
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{ |
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apr_uint32_t prev = val; |
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apr_uint32_t prev = val; |
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Lines 90-107
APR_DECLARE(apr_uint32_t) apr_atomic_xch
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return prev; |
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return prev; |
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} |
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} |
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APR_DECLARE(void*) apr_atomic_casptr(volatile void **mem, void *with, const void *cmp) |
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APR_DECLARE(void*) apr_atomic_casptr(void **mem, void *with, void *cmp) |
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{ |
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{ |
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void *prev; |
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void *prev; |
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#if APR_SIZEOF_VOIDP == 4 |
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#if APR_SIZEOF_VOIDP == 4 |
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asm volatile ("lock; cmpxchgl %2, %1" |
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asm volatile ("lock; cmpxchgl %2, %1" |
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: "=a" (prev), "=m" (*mem) |
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: "=a" (prev), "=m" (*mem) |
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: "r" (with), "m" (*mem), "0" (cmp)); |
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: "r" (with), "m" (*mem), "0" (cmp) |
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: "memory"); |
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#elif APR_SIZEOF_VOIDP == 8 |
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#elif APR_SIZEOF_VOIDP == 8 |
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asm volatile ("lock; cmpxchgq %q2, %1" |
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asm volatile ("lock; cmpxchgq %q2, %1" |
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: "=a" (prev), "=m" (*mem) |
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: "=a" (prev), "=m" (*mem) |
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: "r" ((unsigned long)with), "m" (*mem), |
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: "r" ((unsigned long)with), "m" (*mem), |
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"0" ((unsigned long)cmp)); |
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"0" ((unsigned long)cmp) |
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: "memory"); |
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#else |
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#else |
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#error APR_SIZEOF_VOIDP value not supported |
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#error APR_SIZEOF_VOIDP value not supported |
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#endif |
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#endif |