Index: apr/atomic/unix/ppc.c =================================================================== --- apr.orig/atomic/unix/ppc.c +++ apr/atomic/unix/ppc.c @@ -18,37 +18,52 @@ #ifdef USE_ATOMICS_PPC +#ifdef HAVE_POWER4_LWSYNC +/* Lightweight Sync (POWER4 new instruction) */ +# define PPC_SYNC " lwsync\n" +#else +# define PPC_SYNC " sync\n" +#endif + #ifdef PPC405_ERRATA # define PPC405_ERR77_SYNC " sync\n" #else # define PPC405_ERR77_SYNC #endif +#define barrier() asm volatile ("sync" : : : "memory") + APR_DECLARE(apr_status_t) apr_atomic_init(apr_pool_t *p) { return APR_SUCCESS; } -APR_DECLARE(apr_uint32_t) apr_atomic_read32(volatile apr_uint32_t *mem) +APR_DECLARE(apr_uint32_t) apr_atomic_read32(apr_uint32_t *mem) { + barrier(); + return *mem; } -APR_DECLARE(void) apr_atomic_set32(volatile apr_uint32_t *mem, apr_uint32_t val) +APR_DECLARE(void) apr_atomic_set32(apr_uint32_t *mem, apr_uint32_t val) { *mem = val; + + barrier(); } -APR_DECLARE(apr_uint32_t) apr_atomic_add32(volatile apr_uint32_t *mem, apr_uint32_t val) +APR_DECLARE(apr_uint32_t) apr_atomic_add32(apr_uint32_t *mem, apr_uint32_t val) { apr_uint32_t prev, temp; - asm volatile ("loop_%=:\n" /* lost reservation */ + asm volatile (PPC_SYNC + "loop_%=:\n" /* lost reservation */ " lwarx %0,0,%3\n" /* load and reserve */ " add %1,%0,%4\n" /* add val and prev */ PPC405_ERR77_SYNC /* ppc405 Erratum 77 */ " stwcx. %1,0,%3\n" /* store new value */ " bne- loop_%=\n" /* loop if lost */ + " isync\n" /* memory barrier */ : "=&r" (prev), "=&r" (temp), "=m" (*mem) : "b" (mem), "r" (val) : "cc", "memory"); @@ -56,31 +71,35 @@ APR_DECLARE(apr_uint32_t) apr_atomic_add return prev; } -APR_DECLARE(void) apr_atomic_sub32(volatile apr_uint32_t *mem, apr_uint32_t val) +APR_DECLARE(void) apr_atomic_sub32(apr_uint32_t *mem, apr_uint32_t val) { apr_uint32_t temp; - asm volatile ("loop_%=:\n" /* lost reservation */ + asm volatile (PPC_SYNC + "loop_%=:\n" /* lost reservation */ " lwarx %0,0,%2\n" /* load and reserve */ " subf %0,%3,%0\n" /* subtract val */ PPC405_ERR77_SYNC /* ppc405 Erratum 77 */ " stwcx. %0,0,%2\n" /* store new value */ " bne- loop_%=\n" /* loop if lost */ + " isync\n" /* memory barrier */ : "=&r" (temp), "=m" (*mem) : "b" (mem), "r" (val) : "cc", "memory"); } -APR_DECLARE(apr_uint32_t) apr_atomic_inc32(volatile apr_uint32_t *mem) +APR_DECLARE(apr_uint32_t) apr_atomic_inc32(apr_uint32_t *mem) { apr_uint32_t prev; - asm volatile ("loop_%=:\n" /* lost reservation */ + asm volatile (PPC_SYNC + "loop_%=:\n" /* lost reservation */ " lwarx %0,0,%2\n" /* load and reserve */ " addi %0,%0,1\n" /* add immediate */ PPC405_ERR77_SYNC /* ppc405 Erratum 77 */ " stwcx. %0,0,%2\n" /* store new value */ " bne- loop_%=\n" /* loop if lost */ + " isync\n" /* memory barrier */ " subi %0,%0,1\n" /* return old value */ : "=&b" (prev), "=m" (*mem) : "b" (mem), "m" (*mem) @@ -89,16 +108,18 @@ APR_DECLARE(apr_uint32_t) apr_atomic_inc return prev; } -APR_DECLARE(int) apr_atomic_dec32(volatile apr_uint32_t *mem) +APR_DECLARE(int) apr_atomic_dec32(apr_uint32_t *mem) { apr_uint32_t prev; - asm volatile ("loop_%=:\n" /* lost reservation */ + asm volatile (PPC_SYNC + "loop_%=:\n" /* lost reservation */ " lwarx %0,0,%2\n" /* load and reserve */ " subi %0,%0,1\n" /* subtract immediate */ PPC405_ERR77_SYNC /* ppc405 Erratum 77 */ " stwcx. %0,0,%2\n" /* store new value */ " bne- loop_%=\n" /* loop if lost */ + " isync\n" /* memory barrier */ : "=&b" (prev), "=m" (*mem) : "b" (mem), "m" (*mem) : "cc", "memory"); @@ -106,12 +127,13 @@ APR_DECLARE(int) apr_atomic_dec32(volati return prev; } -APR_DECLARE(apr_uint32_t) apr_atomic_cas32(volatile apr_uint32_t *mem, apr_uint32_t with, +APR_DECLARE(apr_uint32_t) apr_atomic_cas32(apr_uint32_t *mem, apr_uint32_t with, apr_uint32_t cmp) { apr_uint32_t prev; - asm volatile ("loop_%=:\n" /* lost reservation */ + asm volatile (PPC_SYNC + "loop_%=:\n" /* lost reservation */ " lwarx %0,0,%1\n" /* load and reserve */ " cmpw %0,%3\n" /* compare operands */ " bne- exit_%=\n" /* skip if not equal */ @@ -119,6 +141,7 @@ APR_DECLARE(apr_uint32_t) apr_atomic_cas " stwcx. %2,0,%1\n" /* store new value */ " bne- loop_%=\n" /* loop if lost */ "exit_%=:\n" /* not equal */ + " isync\n" /* memory barrier */ : "=&r" (prev) : "b" (mem), "r" (with), "r" (cmp) : "cc", "memory"); @@ -126,15 +149,17 @@ APR_DECLARE(apr_uint32_t) apr_atomic_cas return prev; } -APR_DECLARE(apr_uint32_t) apr_atomic_xchg32(volatile apr_uint32_t *mem, apr_uint32_t val) +APR_DECLARE(apr_uint32_t) apr_atomic_xchg32(apr_uint32_t *mem, apr_uint32_t val) { apr_uint32_t prev; - asm volatile ("loop_%=:\n" /* lost reservation */ + asm volatile (PPC_SYNC + "loop_%=:\n" /* lost reservation */ " lwarx %0,0,%1\n" /* load and reserve */ PPC405_ERR77_SYNC /* ppc405 Erratum 77 */ " stwcx. %2,0,%1\n" /* store new value */ " bne- loop_%=" /* loop if lost */ + " isync\n" /* memory barrier */ : "=&r" (prev) : "b" (mem), "r" (val) : "cc", "memory"); @@ -142,11 +167,12 @@ APR_DECLARE(apr_uint32_t) apr_atomic_xch return prev; } -APR_DECLARE(void*) apr_atomic_casptr(volatile void **mem, void *with, const void *cmp) +APR_DECLARE(void*) apr_atomic_casptr(void **mem, void *with, void *cmp) { void *prev; #if APR_SIZEOF_VOIDP == 4 - asm volatile ("loop_%=:\n" /* lost reservation */ + asm volatile (PPC_SYNC + "loop_%=:\n" /* lost reservation */ " lwarx %0,0,%1\n" /* load and reserve */ " cmpw %0,%3\n" /* compare operands */ " bne- exit_%=\n" /* skip if not equal */ @@ -154,11 +180,13 @@ APR_DECLARE(void*) apr_atomic_casptr(vol " stwcx. %2,0,%1\n" /* store new value */ " bne- loop_%=\n" /* loop if lost */ "exit_%=:\n" /* not equal */ + " isync\n" /* memory barrier */ : "=&r" (prev) : "b" (mem), "r" (with), "r" (cmp) : "cc", "memory"); #elif APR_SIZEOF_VOIDP == 8 - asm volatile ("loop_%=:\n" /* lost reservation */ + asm volatile (PPC_SYNC + "loop_%=:\n" /* lost reservation */ " ldarx %0,0,%1\n" /* load and reserve */ " cmpd %0,%3\n" /* compare operands */ " bne- exit_%=\n" /* skip if not equal */ @@ -166,6 +194,7 @@ APR_DECLARE(void*) apr_atomic_casptr(vol " stdcx. %2,0,%1\n" /* store new value */ " bne- loop_%=\n" /* loop if lost */ "exit_%=:\n" /* not equal */ + " isync\n" /* memory barrier */ : "=&r" (prev) : "b" (mem), "r" (with), "r" (cmp) : "cc", "memory"); Index: apr/configure.in =================================================================== --- apr.orig/configure.in +++ apr/configure.in @@ -401,6 +401,19 @@ case $host in ;; esac +AC_CACHE_CHECK([for POWER4 lwsync mnemonic], [atomic_builtins], +[AC_TRY_RUN([ +int main() +{ + asm volatile ("lwsync" : : : "memory"); + + return 0; +}], [have_lwsync=yes], [have_lwsync=no], [have_lwsync=no])]) + +if test "$have_lwsync" = "yes"; then + AC_DEFINE(HAVE_POWER4_LWSYNC, 1, [Define if target CPU has lwsync]) +fi + dnl Check the depend program we can use APR_CHECK_DEPEND