On a prospective Solaris SPARC 64bit port (see issue 86117), building module
udkapi fails

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idlc: compile 'Exception.idl' ...
dmake:  Error code 138, while making '../../../../unxsols4.pro/ucr/cssuno.db'
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due to a SIGBUS in sal/rtl/source/alloc_cache.c:1.5 code:

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t@1 (l@1) terminated by signal BUS (invalid address alignment)
Current function is rtl_cache_slab_alloc (optimized)
  502                           bufctl->m_next = 0;
(dbx) where
current thread: t@1
=>[1] rtl_cache_slab_alloc(cache = ???) (optimized), at 0xffffffff7d83bbe4 (line
~502) in "alloc_cache.c"
  [2] rtl_cache_alloc(cache = ???) (optimized), at 0xffffffff7d83c7b0 (line
~1260) in "alloc_cache.c"
  [3] rtl_cache_depot_populate(cache = ???) (optimized), at 0xffffffff7d83bf58
(line ~807) in "alloc_cache.c"
  [4] rtl_cache_free(cache = ???, obj = ???) (optimized), at 0xffffffff7d83c8b4
(line ~1320) in "alloc_cache.c"
  [5] rtl_freeMemory(p = ???) (optimized), at 0xffffffff7d83b404 (line ~254) in
"alloc_global.c"
  [6] rtl_string_release(pThis = ???) (optimized), at 0xffffffff7d84777c (line
~1027) in "strtmpl.c"
  [7] rtl_string_newConcat(ppThis = ???, pLeft = ???, pRight = ???) (optimized),
at 0xffffffff7d847b28 (line ~1216) in "strtmpl.c"
  [8] yylex(0x14e0, 0x100151378, 0x100150c38, 0x1001517b2, 0x100152632,
0x10014f730), at 0x100012c00
  [9] yyparse(0x7000, 0x10014f730, 0x0, 0x1001560b0, 0xffffffff7fffa710,
0xffffffff7fffc010), at 0x10001610c
  [10] compileFile(0xffffffff7fffc4b0, 0x100157670, 0xffffffff7cc003c8, 0x24,
0xffffffff7fffc500, 0xffffffff7fffc330), at 0x1000231dc
  [11] 0x10001fe6c(0x100158ef0, 0x0, 0x0, 0xffffffff7fffc4a8,
0xffffffff7fffc4a0, 0xffffffff7fffc500), at 0x10001fe6c
  [12] main(0x2, 0xffffffff7fffc6b8, 0xffffffff7fffc6d0, 0xffffffff7f34ade8,
0xffffffff7e000680, 0xffffffff7e0006c0), at 0x10001fb88
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